A semiconductor device of a related technique is described in Japanese Laid-Open Patent Application JP-2002-170928 (U.S. Pat. No. 6,727,533B2) and Japanese Laid-Open Patent Application JP-2002-093946 (U.S. Pat. No. 6,639,315B2).
Japanese Laid-Open Patent Application JP-2002-170928 discloses a semiconductor device. The semiconductor device has a fine interconnection layer in a semiconductor element, a giant interconnection (super-connect) layer and a switch circuit. In this semiconductor device, an interconnection gap in the super-connect interconnection layer is larger as compared with an interconnection gap in the interconnection layer in the semiconductor element, and thus parasitic capacitance of interconnection is small and electric resistance is low. On the other hand, Japanese Laid-Open Patent Application JP-2002-093946 discloses a semiconductor device and a package structure of the semiconductor device. In this semiconductor device, a thick and low-elasticity stress relaxation layer is provided between a pad on a semiconductor element and a land used for an external terminal, and an electrostatic capacitance between an interconnection in the semiconductor element and an extraction interconnection to the land is reduced by the thick stress relaxation layer.
However, according to the above-mentioned related technique described in Japanese Laid-Open Patent Application JP-2002-170928 and Japanese Laid-Open Patent Application JP-2002-093946, even though the parasitic capacitance between the super-connect interconnections or between top and bottom of the stress relaxation layer can be reduced, an overall structure of the semiconductor element and the super-connect interconnection is not optimized. Therefore, there is a problem in that signal quality is deteriorated, particularly in a case where a high-speed signal over 10 Gbps is to be handled.
As a related technique, Japanese Laid-Open Patent Application JP-2006-32600 (US2006012029(A1)) discloses a semiconductor device. The semiconductor device has: a semiconductor substrate; a fine interconnection structure section in which one or plural first interconnection layers and one or plural first insulating layers are alternately stacked on said semiconductor substrate; a first giant interconnection structure section in which one or plural second interconnection layers and one or plural second insulating layers are alternately stacked on said fine interconnection structure section; and a second giant interconnection structure section in which one or plural third interconnection layers and one or plural third insulating layers are alternately stacked on said first giant interconnection structure section. Said first to third interconnection layers respectively have insulating films and interconnections. Said second insulating layer and said third insulating layer are thicker than said first insulating layer. An elastic modulus of said third insulating layer at 25 degrees centigrade is not more than an elastic modulus of said second insulating layer at 25 degrees centigrade. A thickness of each said third interconnection layer and said second interconnection layer is equal to or more than two times a thickness of said first interconnection layer.
This time, the inventors of the present application have recognized the following points. FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device of a related technique. The semiconductor device of the related technique has semiconductor element interconnections 102 that are provided in a plurality of insulating layers 150 on a semiconductor substrate 101 including transistor circuits (not shown) and are connected through semiconductor element interconnection vias 103. In the semiconductor device, there further exists a top-layer semiconductor element interconnection 104 thereon that is formed by a substantially equivalent process equipment as in the case of the semiconductor element interconnection 102. The top-layer semiconductor element interconnection 104 includes a power source pad 104v, a ground pad 104g, a signal pad 104s and other routed interconnections 104m. The power source pad 104v, the ground pad 104g and the signal pad 104s are substantially the same in size. A under bump metallization (UBM) 106 is formed on the top-layer semiconductor element interconnection 104 through a cover film 105. The power source pad 104v, the ground pad 104g and the signal pad 104s are respectively connected to bumps 107 as external connection terminals.
Here, a reason why the power source pad 104v, the ground pad 104g and the signal pad 104s are substantially the same in size is as follows. For example, let us consider a case where the bump 107 is made of alloy of Sn and Ag, wherein a metal layer is formed in a desired region by plating and then reflow is performed to form the bump 107 having a shape shown in FIG. 1. In this case, if the above-mentioned three kinds of pads are not the same in size, the respective ball-shape bumps 107 including the UBM 106 become different in size, which prevents excellent external connection. The same reason applies to a case where bump material is formed by printing or a spherical ball is transferred. Consequently, the power source pad 104v, the ground pad 104g and the signal pad 104s are substantially the same in size.
However, in a case where the semiconductor device having the structure shown in FIG. 1 according to the related technique operates at ultrahigh speed, particularly over 10 Gbps, the input-output to a signal line becomes unstable and thus signal communication between the semiconductor device and the outside thereof becomes impossible, which is a problem that was first revealed by the inventors as a result of earnest research. At the same time, the reason for this was first revealed by the inventors as a result of the research; that is, coupling capacitance between the signal pad 104s in the top-layer semiconductor element interconnection 104 and the semiconductor element interconnection 102 in the lower layer is large, which deteriorates the signal quality.
One possible solution to solve the problem and to reduce the parasitic capacitance is to use the super-connect technology in which thicknesses of an interconnection and an insulating film are several times (e.g. three to ten times) larger than those of a semiconductor element interconnection and a semiconductor element insulating film, respectively. FIG. 2 is a cross-sectional view showing a configuration in which the super-connect technology is applied to the semiconductor device of the related technique. In this case, a thick super-connect insulating film 109 and a thick super-connect interconnection 110 (connected to the top-layer semiconductor element interconnection 104 through a super-connect via 108) are merely formed on the top-layer semiconductor element interconnection 104. Therefore, although parasitic capacitance between the super-connect interconnection 110 and another portion through the super-connect insulating film 109 is reduced, there still remains the essential problem, namely the large parasitic capacitance between the signal pad 104s and the semiconductor element interconnection 102 in the lower layer, which does not improve the deterioration of the transmission characteristics.